ASIC DESIGN VERIFICATION ENGINEER
4 H1B filings at Marvell Semiconductor in FY2017
4
Total Filings
$96,910
Median Salary
100.0%
Approval Rate
4
Certified (0 denied)
Salary Distribution
Range shows where 80% of salaries fall. The marker indicates the median.
Range: $94,319 - $99,500
Salary Frequency
Hover over bars to see exact counts. Salary ranges in $25K increments.
Work Locations
SANTA CLARA, CA
4 filings
All Filings (4)
| Job Title | Location | Salary | Year | Status | View |
|---|---|---|---|---|---|
| ASIC DESIGN VERIFICATION ENGINEER 17-2072 | Santa Clara, CA | $99,500 | FY2017 | CERTIFIED | View |
| ASIC DESIGN VERIFICATION ENGINEER 17-2072 | Santa Clara, CA | $94,319 | FY2017 | CERTIFIED | View |
| ASIC DESIGN VERIFICATION ENGINEER 17-2072 | Santa Clara, CA | $94,319 | FY2017 | CERTIFIED | View |
| ASIC DESIGN VERIFICATION ENGINEER 17-2072 | Santa Clara, CA | $99,500 | FY2017 | CERTIFIED | View |