ASIC DESIGN VERIFICATION ENGINEER
5 H1B filings at Marvell Semiconductor in FY2016
5
Total Filings
$88,423
Median Salary
100.0%
Approval Rate
5
Certified (0 denied)
Salary Distribution
Range shows where 80% of salaries fall. The marker indicates the median.
Range: $88,423 - $89,556
Salary Frequency
Hover over bars to see exact counts. Salary ranges in $25K increments.
Work Locations
SANTA CLARA, CA
5 filings
All Filings (5)
| Job Title | Location | Salary | Year | Status | View |
|---|---|---|---|---|---|
| ASIC DESIGN VERIFICATION ENGINEER 17-2071 | Santa Clara, CA | $88,423 | FY2016 | CERTIFIED | View |
| ASIC DESIGN VERIFICATION ENGINEER 17-2072 | Santa Clara, CA | $89,556 | FY2016 | CERTIFIED | View |
| ASIC DESIGN VERIFICATION ENGINEER 17-2072 | Santa Clara, CA | $89,556 | FY2016 | CERTIFIED | View |
| ASIC DESIGN VERIFICATION ENGINEER 17-2071 | Santa Clara, CA | $88,423 | FY2016 | CERTIFIED | View |
| ASIC DESIGN VERIFICATION ENGINEER 17-2072 | Santa Clara, CA | $88,423 | FY2016 | CERTIFIED | View |
ASIC DESIGN VERIFICATION ENGINEER CERTIFIED
Santa Clara, CA $88,423 FY2016
ASIC DESIGN VERIFICATION ENGINEER CERTIFIED
Santa Clara, CA $89,556 FY2016
ASIC DESIGN VERIFICATION ENGINEER CERTIFIED
Santa Clara, CA $89,556 FY2016
ASIC DESIGN VERIFICATION ENGINEER CERTIFIED
Santa Clara, CA $88,423 FY2016
ASIC DESIGN VERIFICATION ENGINEER CERTIFIED
Santa Clara, CA $88,423 FY2016